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TAS5152
SLES127 - FEBRUARY 2005
TM
STEREO DIGITAL AMPLIFIER POWER STAGE
FEATURES D 2x125 W at 10% THD+N Into 4-W BTL D 2x98 W at 10% THD+N Into 6-W BTL D 2x76 W at 10% THD+N Into 8-W BTL D 4x45 W at 10% THD+N Into 3-W SE D 4x35 W at 10% THD+N Into 4-W SE D 1x192 W at 10% THD+N Into 3-W PBTL D 1x240 W at 10% THD+N Into 2-W PBTL D >100 dB SNR (A-Weighted) D <0.1% THD+N at 1 W D Thermally Enhanced Package Option:
- DKD (36-Pin PSOP3) A low-cost, high-fidelity audio system can be built using a TI chipset, comprised of a modulator (e.g., TAS5508) and the TAS5152. This system only requires a simple passive LC demodulation filter to deliver high-quality, high-efficiency audio amplification with proven EMI compliance. This device requires two power supplies, 12 V for GVDD and VDD, and 35 V for PVDD. The TAS5152 does not require power-up sequencing due to internal power-on reset. The efficiency of this digital amplifier is greater than 90% into 6 , which enables the use of smaller power supplies and heatsinks. The TAS5152 has an innovative protection system integrated on-chip, safeguarding the device against a wide range of fault conditions that could damage the system. These safeguards are short-circuit protection, overcurrent protection, undervoltage protection, and overtemperature protection. The TAS5152 has a new proprietary current-limiting circuit that reduces the possibility of device shutdown during high-level music transients. A new programmable overcurrent detector allows the use of lower-cost inductors in the demodulation output filter.
BTL OUTPUT POWER vs SUPPLY VOLTAGE
130 120 110 100 PO - Output Power - W 90 80 70 60 50 40 30 20 10 0 0 5 10 15 20 25 30 35 PVDD - Supply Voltage - V 8 6 4 TC = 75C THD+N @ 10%
D High-Efficiency Power Stage (>90%) With
140-mW Output MOSFETs
D Power-On Reset for Protection on Power Up
Without Any Power-Supply Sequencing
D Integrated Self-Protection Circuits Including:
- - - - Undervoltage Overtemperature Overload Short Circuit
D Error Reporting D EMI Compliant When Used With
Recommended System Design
D Intelligent Gate Drive APPLICATIONS D Mini/Micro Audio System D DVD Receiver D Home Theater DESCRIPTION
The TAS5152 is a third-generation, high-performance, integrated stereo digital amplifier power stage with improved protection system. The TAS5152 is capable of driving a 4- bridge-tied load (BTL) at up to 125 W per channel with low integrated noise at the output, low THD+N performance, and low idle power dissipation.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PurePath Digital and PowerPAD are trademarks of Texas Instruments. Other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2005, Texas Instruments Incorporated
TAS5152
SLES127 - FEBRUARY 2005
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
GENERAL INFORMATION
The TAS5152 is available in a 36-pin PSOP3 (DKD) thermally enhanced package. The package contains a heat slug that is located on the top side of the device for convenient thermal coupling to the heatsink.
MODE Selection Pins
MODE PINS M3 0 M2 0 0 1 M1 0 1 0 2N (1) AD/BD modulation Reserved 1N (1) AD modulation 1N (1) AD modulation PWM INPUT OUTPUT CONFIGURATION 2 channels BTL output PROTECTION SCHEME
BTL mode (2)
DKD PACKAGE (TOP VIEW)
0 0
2 channels BTL output 1 channel PBTL output
BTL mode (2) PBTL mode. Only PWM_A input is used. Protection works similarly to BTL mode (2). Only difference in SE mode is that OUT_x is Hi-Z instead of a pulldown through internal pulldown resistor.
GVDD_B OTW SD PWM_A RESET_AB PWM_B OC_ADJ GND AGND VREG M3 M2 M1 PWM_C RESET_CD PWM_D VDD GVDD_C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
GVDD_A BST_A PVDD_A OUT_A GND_A GND_B OUT_B PVDD_B BST_B BST_C PVDD_C OUT_C GND_C GND_D OUT_D PVDD_D BST_D GVDD_D
0
1
1
1
0
0
1N (1) AD modulation
4 channels SE output
1 1
0 1
1 0 Reserved
1 1 1 (1) The 1N and 2N naming convention is used to indicate the required number of PWM lines to the power stage per channel in a specific mode. (2) An overload protection (OLP) occurring on A or B causes both channels to shut down. An OLP on C or D works similarly. Global errors like overtemperature error (OTE), undervoltage protection (UVP) and power-on reset (POR) affect all channels.
Package Heat Dissipation Ratings (1)
PARAMETER RJC (C/W)--2 BTL or 4 SE channels (8 transistors) RJC C/W)--1 BTL or 2 SE channel(s) (4 transistors) RJC (C/W)--(1 transistor) Pad area (2) TAS5152DKD 1.28 2.56 8.6 80 mm2
(1) JC is junction-to-case, CH is case-to-heatsink. (2) RCH is an important consideration. Assume a 2-mil thickness of typical thermal grease between the pad area and the heatsink. The RCH with this condition is 0.8C/W for the DKD package and 1.8C/W for the DDV package.
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TAS5152
SLES127 - FEBRUARY 2005
Absolute Maximum Ratings
over operating free-air temperature range unless otherwise noted(1) TAS5152 VDD to AGND GVDD_X to AGND PVDD_X to GND_X (2) OUT_X to GND_X (2) BST_X to GND_X (2) VREG to AGND GND_X to GND GND_X to AGND GND to AGND PWM_X, OC_ADJ, M1, M2, M3 to AGND RESET_X, SD, OTW to AGND Maximum continuous sink current (SD, OTW) Maximum operating junction temperature range, TJ Storage temperature Lead temperature, 1,6 mm (1/16 inch) from case for 10 seconds Minimum pulse width low -0.3 V to 13.2 V -0.3 V to 13.2 V -0.3 V to 50 V -0.3 V to 50 V -0.3 V to 63.2 V -0.3 V to 4.2 V -0.3 V to 0.3 V -0.3 V to 0.3 V -0.3 V to 0.3 V -0.3 V to 4.2 V -0.3 V to 7 V 9 mA 0C to 125C -40_C to 125_C 260_C 50 ns
Ordering Information
TA 0C to 70C PACKAGE TAS5152DKD DESCRIPTION 36-pin PSOP3
For the most current specification and package information, see the TI Web site at www.ti.com.
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability. (2) These voltages represent the dc voltage + peak ac waveform measured at the terminal of the device in all conditions.
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TAS5152
SLES127 - FEBRUARY 2005
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Terminal Functions
TERMINAL NAME AGND BST_A BST_B BST_C BST_D GND GND_A GND_B GND_C GND_D GVDD_A GVDD_B GVDD_C GVDD_D M1 M2 M3 OC_ADJ OTW OUT_A OUT_B OUT_C OUT_D PVDD_A PVDD_B PVDD_C PVDD_D PWM_A PWM_B PWM_C PWM_D RESET_AB RESET_CD SD VDD NO. 9 35 28 27 20 8 32 31 24 23 36 1 18 19 13 12 11 7 2 33 30 25 22 34 29 26 21 4 6 14 16 5 15 3 17 FUNCTION FUNCTION (1) P P P P P P P P P P P P P P I I I O O O O O O P P P P I I I I I I O P P Analog ground HS bootstrap supply (BST), external capacitor to OUT_A required HS bootstrap supply (BST), external capacitor to OUT_B required HS bootstrap supply (BST), external capacitor to OUT_C required HS bootstrap supply (BST), external capacitor to OUT_D required Ground Power ground for half-bridge A Power ground for half-bridge B Power ground for half-bridge C Power ground for half-bridge D Gate-drive voltage supply requires 0.1-F capacitor to AGND Gate-drive voltage supply requires 0.1-F capacitor to AGND Gate-drive voltage supply requires 0.1-F capacitor to AGND Gate-drive voltage supply requires 0.1-F capacitor to AGND Mode selection pin Mode selection pin Mode selection pin Analog overcurrent programming pin requires resistor to ground Overtemperature warning signal, open drain, active-low Output, half-bridge A Output, half-bridge B Output, half-bridge C Output, half-bridge D Power supply input for half-bridge A requires close decoupling of 0.1-F capacitor to GND_A Power supply input for half-bridge B requires close decoupling of 0.1-F capacitor to GND_B Power supply input for half-bridge C requires close decoupling of 0.1-F capacitor to GND_C Power supply input for half-bridge D requires close decoupling of 0.1-F capacitor to GND_D Input signal for half-bridge A Input signal for half-bridge B Input signal for half-bridge C Input signal for half-bridge D Reset signal for half-bridge A and half-bridge B, active-low Reset signal for half-bridge C and half-bridge D, active-low Shutdown signal, open drain, active-low Power supply for digital voltage regulator requires 0.1-F capacitor to GND. Digital regulator supply filter pin requires 0.1-F capacitor to AGND DESCRIPTION
VREG 10 (1) I = input, O = Output, P = Power
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TAS5152
SLES127 - FEBRUARY 2005
SYSTEM BLOCK DIAGRAM
OTW System Microcontroller SD
OTW
SD
TAS5508
BST_A BST_B Bootstrap Capacitors
VALID
RESET_AB RESET_CD PWM_A
OUT_A Input H-Bridge 1 2-Channel H-Bridge BTL Mode Output H-Bridge 1 OUT_B
LeftChannel Output
PWM_B
2nd-Order L-C Output Filter for Each Half-Bridge
PWM_C RightChannel Output Input H-Bridge 2 GVDD_A, B, C, D
OUT_C Output H-Bridge 2 OUT_D
PWM_D M1 Hardwire Mode Control M2 M3
2nd-Order L-C Output Filter for Each Half-Bridge
PVDD_A, B, C, D
GND_A, B, C, D
BST_C OC_ADJ BST_D Bootstrap Capacitors
4
4
4 GVDD VDD VREG Power Supply Decoupling
35 V System Power Supply GND
PVDD
PVDD Power Supply Decoupling
AGND
VREG
GND
VDD
Hardwire OC Limit
GND
12 V
GVDD (12 V)/VDD (12 V)
VAC
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TAS5152
SLES127 - FEBRUARY 2005
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FUNCTIONAL BLOCK DIAGRAM
VDD OTW
Internal Pullup Resistors to VREG
Undervoltage Protection
4 VREG VREG
SD M1 M2 M3 Protection and I/O Logic
Power On Reset
AGND
Temp. Sense
GND
RESET_AB RESET_CD Overload Protection Isense OC_ADJ GVDD_D BST_D PVDD_D PWM_D PWM Rcv. Ctrl. Timing Gate Drive
BTL/PBTL-Configuration Pulldown Resistor
OUT_D
GND_D GVDD_C BST_C PVDD_C PWM_C PWM Rcv. Ctrl. Timing Gate Drive
BTL/PBTL-Configuration Pulldown Resistor
OUT_C
GND_C GVDD_B BST_B PVDD_B PWM_B PWM Rcv. Ctrl. Timing Gate Drive
BTL/PBTL-Configuration Pulldown Resistor
OUT_B
GND_B GVDD_A BST_A PVDD_A PWM_A PWM Rcv. Ctrl. Timing Gate Drive
BTL/PBTL-Configuration Pulldown Resistor
OUT_A
GND_A
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TAS5152
SLES127 - FEBRUARY 2005
RECOMMENDED OPERATING CONDITIONS
CONDITIONS PVDD_x GVDD_x VDD RL (BTL) RL (SE) RL (PBTL) LOutput (BTL) LOutput (SE) Output-filter Output-filter inductance LOutput (PBTL) FPWM TJ PWM frame rate Junction temperature Half-bridge supply Supply for logic regulators and gate-drive circuitry Digital regulator input DC supply voltage DC supply voltage DC supply voltage Output filter: L = 10 H, C = 470 nF Output AD modulation, switching frequency > 350 kHz Minimum output inductance under short-circuit condition 192 0 MIN 0 10.8 10.8 3 2 1.5 NOM 35 12 12 4 3 2 10 10 10 384 432 125 kHz _C H MAX 37 13.2 13.2 UNIT V V V
Load impedance
AUDIO SPECIFICATIONS (BTL)
PVDD_X = 35 V, GVDD = VDD = 12 V, BTL mode, RL = 4 , audio frequency = 1 kHz, AES17 filter, FPWM = 384 kHz, case temperature = 75C, unless otherwise noted. Audio performance is recorded as a chipset, using TAS5508 PWM processor with an effective modulation index limit of 96.1%. All performance is in accordance with recommended operating conditions unless otherwise specified. TAS5152 SYMBOL PARAMETER CONDITIONS RL = 4 ,10% THD, clipped input signal RL = 6 ,10% THD, clipped input signal RL = 8 ,10% THD, clipped input signal Po Power output per channel RL = 4 , 0 dBFS, unclipped input signal RL = 6 , 0 dBFS, unclipped input signal RL = 8 , 0 dBFS, unclipped input signal 0 dBFS THD+N Vn SNR Total harmonic distortion + noise Output integrated noise Signal-to-noise ratio (1) 1W A-weighted A-weighted A-weighted, input level = -60 dBFS using TAS5508 modulator DNR Dynamic range A-weighted, input level = -60 dBFS using TAS5518 modulator MIN TYP 125 98 76 W 96 72 57 0.3 0.1 145 102 102 110 2 % V dB dB dB W MAX UNIT
Pidle Power dissipation due to idle losses (IPVDDx) PO = 0 W, 2 channels switching (2) (1) SNR is calculated relative to 0-dBFS input level. (2) Actual system idle losses are affected by core losses of output inductors.
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TAS5152
SLES127 - FEBRUARY 2005
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AUDIO SPECIFICATIONS (Single-Ended Output)
PVDD_X = 35 V, GVDD = VDD = 12 V, SE mode, RL = 4 , audio frequency = 1 kHz, AES17 filter, FPWM = 384 kHz, case temperature = 75C, unless otherwise noted. Audio performance is recorded as a chipset, using TAS5086 PWM processor with an effective modulation index limit of 96.1%. All performance is in accordance with recommended operating conditions unless otherwise specified. TAS5152 SYMBOL PARAMETER CONDITIONS RL = 3 ,10% THD, clipped input signal RL = 4 ,10% THD, clipped input signal Po Power output per channel RL = 3 , 0 dBFS, unclipped input signal RL = 4 , 0 dBFS, unclipped input signal 0 dBFS THD+N Vn SNR DNR Total harmonic distortion + noise Output integrated noise Signal-to-noise ratio (1) Dynamic range 1W A-weighted A-weighted A-weighted, input level = -60 dBFS using TAS5508 modulator PO = 0 W, 4 channels switching (2) MIN TYP 45 35 W 35 25 0.2 0.1 90 100 100 2 % V dB dB W MAX UNIT
Pidle Power dissipation due to idle losses (IPVDDx) (1) SNR is calculated relative to 0-dBFS input level. (2) Actual system idle losses are affected by core losses of output inductors.
AUDIO SPECIFICATIONS (PBTL)
PVDD_X = 35 V, GVDD = VDD = 12 V, PBTL mode, RL = 3 , audio frequency = 1 kHz, AES17 filter, FPWM = 384 kHz, case temperature = 75C, unless otherwise noted. Audio performance is recorded as a chipset, using TAS5508 PWM processor with an effective modulation index limit of 96.1%. All performance is in accordance with recommended operating conditions unless otherwise specified. TAS5152 SYMBOL PARAMETER CONDITIONS RL = 3 ,10% THD, clipped input signal RL = 2 ,10% THD, clipped input signal Po Power output per channel RL = 3 , 0 dBFS, unclipped input signal RL = 2 , 0 dBFS, unclipped input signal 0 dBFS THD+N Vn SNR Total harmonic distortion + noise Output integrated noise Signal-to-noise ratio (1) 1W A-weighted A-weighted A-weighted, input level = -60 dBFS using TAS5508 modulator DNR Dynamic range A-weighted, input level = -60 dBFS using TAS5518 modulator MIN TYP 192 240 W 145 190 0.2 0.1 160 102 102 110 2 % V dB dB dB W MAX UNIT
Pidle Power dissipation due to idle losses (IPVDDx) PO = 0 W, 1 channel switching (2) (1) SNR is calculated relative to 0-dBFS input level. (2) Actual system idle losses are affected by core losses of output inductors.
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TAS5152
SLES127 - FEBRUARY 2005
ELECTRICAL CHARACTERISTICS
RL= 4 . FPWM = 384 kHz, unless otherwise noted. All performance is in accordance with recommended operating conditions unless otherwise specified. SYMBOL PARAMETER CONDITIONS TAS5152 MIN 3 TYP 3.3 7 6 5 0.3 15 7 MAX 3.6 17 11 16 1 25 25 mA mA A mA UNITS V
Internal Voltage Regulator and Current Consumption VREG IVDD IGVDD_x Voltage regulator, only used as a reference node VDD supply current Gate supply current per half-bridge VDD = 12 V Operating, 50% duty cycle Idle, reset mode 50% duty cycle Reset mode 50% duty cycle, without output filter or load Reset mode, no switching Output Stage MOSFETs RDSon,LS Drain-to-source resistance, LS TJ= 25C, includes metallization resistance, GVDD = 12 V TJ= 25C, includes metallization resistance, GVDD = 12 V 140 155 m
IPVDD_x
Half-bridge idle current
RDSon,HS
Drain-to-source resistance, HS
140
155
m
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TAS5152
SLES127 - FEBRUARY 2005
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ELECTRICAL CHARACTERISTICS (continued)
RL= 4 . FPWM = 384 kHz, unless otherwise noted. All performance is in accordance with recommended operating conditions unless otherwise specified. SYMBOL I/O Protection PARAMETER CONDITIONS TAS5152 MIN TYP 9.8 250 115 125 25 145 155 30 25 Fpwm = 384 kHz Resistor-programmable, high end, ROCP = 15 k Resistor tolerance = 5% Connected when RESET is active to provide bootstrap capacitor charge. Not used in SE mode 1.25 8.5 10.8 210 15 69 11.8 165 135 MAX UNITS V mV _C _C _C _C _C ms A ns k
Vuvp,G Undervoltage protection limit, GVDD_x Vuvp,hyst(1) Undervoltage protection hysteresis
OTW(1) Overtemperature warning Temperature drop needed below OTW temp. for OTWHYST(1) OTW to be inactive after the OTW event OTE(1) Overtemperature error
OTE-OTW OTE-OTW differential differential(1) Temperature drop needed below OTE temp. for OTEHYST(1) SD to be released following an OTE event OLPC IOC IOCT ROCP RPD Overload protection counter Overcurrent limit protection Overcurrent response time OC programming resistor range Internal pulldown resistor at the output of each half-bridge
2.5
k
Static Digital Specifications VIH VIL Leakage High-level input voltage Low-level input voltage Input leakage current Internal pullup resistance, OTW to VREG, SD to VREG Internal pullup resistor VOH High-level output voltage External pullup of 4.7 k to 5V IO = 4 mA No external pullup PWM_A, PWM_B, PWM_C, PWM_D, M1, M2, M3, RESET_AB, RESET_CD 2 0.8 -10 10 V V A
OTW/SHUTDOWN (SD) RINT_PU 20 3 4.5 0.2 30 26 3.3 32 3.6 5 0.4 V V
Devices
k
VOL Low-level output voltage FANOUT Device fanout OTW , SD (1) Specified by design
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TAS5152
SLES127 - FEBRUARY 2005
TYPICAL CHARACTERISTICS, BTL CONFIGURATION
TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER
130 THD+N - Total Harmonic Distortion + Noise - % 10 TC = 75C PVDD = 35 V One Channel PO - Output Power - W 120 110 100 1 90 80 70 60 50 40 30 8 0.01 1 10 PO - Output Power - W 100 20 10 0 0 5
OUTPUT POWER vs SUPPLY VOLTAGE
TC = 75C THD+N @ 10%
4
4
6
6
0.1
8
10
15
20
25
30
35
PVDD - Supply Voltage - V
Figure 1
Figure 2
UNCLIPPED OUTPUT POWER vs SUPPLY VOLTAGE
130 120 110 100 PO - Output Power - W 90 80 70 60 50 40 30 20 10 0 0 5 10 15 20 25 30 35 PVDD - Supply Voltage - V 8 6 4 Efficiency - % 80 70 60 50 40 30 20 10 0 0 25 50 TC = 75C 100 90
SYSTEM EFFICIENCY vs OUTPUT POWER
8
6
4
TC = 25C Two Channels 75 100 125 150 175 200 225 250 PO - Output Power - W
Figure 3
Figure 4
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TAS5152
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SYSTEM POWER LOSS vs OUTPUT POWER
50 45 40 35 Power Loss - W 30 25 20 15 10 5 0 0 25 50 75 100 125 150 175 200 225 250 PO - Output Power - W 8 6 PO - Output Power - W 4 TC = 25C 150 140 130 120 110 100 90 80 70 60 50 40 30 20 10 0 10 20
SYSTEM OUTPUT POWER vs CASE TEMPERATURE
4 6
8
THD+N @10% 30 40 50 60 70 80 90 100 110 120
TC - Case Temperature - C
Figure 5
Figure 6
NOISE AMPLITUDE vs FREQUENCY
0 -10 -20 -30 Noise Amplitude - dBr -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 0 2 4 6 8 10 12 14 16 18 20 22 f - Frequency - kHz TC = 75C -60 dB 1 kHz
Figure 7
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TAS5152
SLES127 - FEBRUARY 2005
TYPICAL CHARACTERISTICS, SE CONFIGURATION
TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER
50 THD+N - Total Harmonic Distortion + Noise - % 10 TC = 75C PVDD = 35 V One Channel PO - Output Power - W 45 40 35 30 25 20 15 10 5 0.01 1 10 PO - Output Power - W 50 0 0 5
OUTPUT POWER vs SUPPLY VOLTAGE
TC = 75C THD+N @ 10%
1 3
3
0.1 4
4
10
15
20
25
30
35
PVDD - Supply Voltage - V
Figure 8
Figure 9
OUTPUT POWER vs CASE TEMPERATURE
60 55 50 PO - Output Power - W 45 40 35 30 25 20 15 10 5 0 10 20 30 40 50 60 70 80 90 100 110 120 TC - Case Temperature - C THD+N@ 10% 4 3
Figure 10
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TAS5152
SLES127 - FEBRUARY 2005
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TYPICAL CHARACTERISTICS, PBTL CONFIGURATION
TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER
260 THD+N - Total Harmonic Distortion + Noise - % 10 TC = 75C PVDD = 35 V One Channel PO - Output Power - W 240 220 200 180 160 140 120 100 80 60 40 20 0.01 1 10 PO - Output Power - W 100 300 0 0 5
OUTPUT POWER vs SUPPLY VOLTAGE
TC = 75C THD+N @ 10%
1 2
2
0.1 3
3
10
15
20
25
30
35
PVDD - Supply Voltage - V
Figure 11
SYSTEM OUTPUT POWER vs CASE TEMPERATURE
300 THD+N @ 10% 280 260 PO - Output Power - W 240 220 200 180 160 140 120 100 10 20 30 40 50 60 70 80 90 100 110 120 TC - Case Temperature - C 3 2
Figure 12
Figure 13
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TAS5152
SLES127 - FEBRUARY 2005
PVDD 10 100 nF 47 F 50 V TAS5152DKD 100 nF 3.3 10 nF 50 V 1000 F 50 V 10 nF 50 V 100 nF 50 V 10 H@10 A 470 nF 100 V 3.3
GVDD 10 F 10 36 35 OTW SD PWM_A 5 6 PWM_M_1 22 k PWM_P_2 7 8 GND 9 PWM_M_2 10 100 nF 11 VREG M3 M2 M1 PWM_C RESET_CD 16 1 GVDD 10 F 10 100 nF PWM_D 17 VDD 18 GVDD_C 100 nF GVDD_D 100 nF BST_D 19 PVDD_D 20 BST_C 26 PVDD_C 25 OUT_C 24 GND_C 23 GND_D 22 OUT_D 21 AGND BST_B 27 PVDD_B 28 PWM_B OC_ADJ GND_B 30 OUT_B 29 RESET_AB BST_A 34 PVDD_A 33 OUT_A 32 GND_A 31
Microcontroller 0 Optional BKND_ERR
1 2 3 4
GVDD_B
GVDD_A
33 nF 100 nF 50 V
PWM_P_1 VALID
10 H@10 A 100 nF 50 V
3.3 10 nF 50 V
33 nF
100 nF 50 V 100 nF 50 V
47 F 50 V 47 F 50 V 100 nF 50 V
10 nF 50 V 3.3
33 nF
TAS5508
12 13 14 15
10 H@10 A 470 nF 100 V
10 H@10 A 100 nF 50 V
100 nF 50 V 33 nF
47 F 50 V
3.3 10 nF 50 V PVDD
3.3 10 nF 50 V 1000 F 50 V
10
Figure 14. Typical Differential (2N) BTL Application With AD Modulation Filters
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TAS5152
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PVDD 10 GVDD 10 F 10 TAS5152DKD 100 nF Microcontroller 0 Optional BKND_ERR 4 PWM_P_1 VALID No connect 22 k 5 6 PWM_B 7 8 GND 9 PWM_P_2 100 nF 10 VREG 11 M3 M2 M1 PWM_C RESET_CD 16 1 GVDD 10 F 10 100 nF No connect 17 VDD 18 GVDD_C 100 nF GVDD_D 100 nF 10 nF 50 V 3.3 1000 F 50 V BST_D 19 33 nF PWM_D PVDD_D 20 100 nF 50 V BST_C 26 PVDD_C 25 OUT_C 24 GND_C 23 GND_D 22 OUT_D 21 47 F 50 V 50 nF 100 V 10 H@10 A 10 H@10 A 470 nF 100 V 33 nF AGND BST_B 27 PVDD_B 28 33 nF 100 nF 50 V 100 nF 50 V 47 F 50 V 47 F 50 V 100 nF 50 V OC_ADJ GND_B 30 OUT_B 29 PWM_A RESET_AB OUT_A 32 GND_A 31 100 nF 50 V 1 2 3 GVDD_B OTW SD GVDD_A BST_A 34 PVDD_A 33 10 H@10 A 100 nF 50 V 36 35 33 nF 10 H@10 A 470 nF 100 V 100 nF 50 V 100 nF 47 F 50 V 3.3 10 nF 50 V 1000 F 50 V
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10 nF 50 V 3.3
3.3 10 nF 50 V
10 nF 50 V 3.3
TAS5508
12 13 14 15
3.3 10 nF 50 V PVDD
10
Figure 15. Typical Non-Differential (1N) BTL Application With AD Modulation Filters
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TAS5152
SLES127 - FEBRUARY 2005
10 100 nF 47 F 50 V TAS5152DKD 100 nF 3.3 10 nF 50 V 33 nF 100 nF 50 V 10 H@10 A A 1000 F 50 V PVDD
GVDD 10 F 10 36 35 OTW SD PWM_A 5 6 PWM_P_2 39 k PWM_P_3 7 8 GND 9 PWM_P_4 100 nF 10 VREG 11 BST_C 26 PVDD_C 25 OUT_C 24 GND_C 23 GND_D 22 RESET_CD 16 1 GVDD 10 F 10 100 nF PWM_D 17 VDD 18 GVDD_C 100 nF GVDD_D BST_D 19 100 nF PVDD_D 20 OUT_D 21 M3 M2 M1 PWM_C AGND BST_B 27 PVDD_B 28 PWM_B OC_ADJ GND_B 30 OUT_B 29 RESET_AB BST_A 34 PVDD_A 33 OUT_A 32 GND_A 31
Microcontroller 0 Optional BKND_ERR
1 2 3 4
GVDD_B
GVDD_A
PWM_P_1 VALID
10 H@10 A B
33 nF
100 nF 50 V 100 nF 50 V
47 F 50 V 47 F 50 V
33 nF
TAS5508
12 13 14 15
10 H@10 A
C
10 H@10 A D 47 F 50 V
100 nF 50 V 33 nF
PVDD 3.3 10 nF 50 V 1000 F 50 V
10
100 nF 100 V A 2.7 k PVDD PVDD/2 220 F 50 V 220 F 50 V
10 nF 50 V 3.3 C 10 nF @ 50 V 2.7 k PVDD 3.3 PVDD/2 220 F 50 V 220 F 50 V
100 nF 100 V
10 nF 50 V 3.3 10 nF @ 50 V
1 F 50 V 100 nF 100 V
1 F 50 V 100 nF 100 V
3.3
100 nF 100 V B 2.7 k PVDD PVDD/2 220 F 50 V 220 F 50 V
10 nF 50 V 3.3 D 10 nF @ 50 V 2.7 k PVDD 3.3 PVDD/2 220 F 50 V 220 F 50 V
100 nF 100 V
10 nF 50 V 3.3 10 nF @ 50 V
1 F 50 V 100 nF 100 V
1 F 50 V 100 nF 100 V
3.3
Figure 16. Typical SE Application
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TAS5152
SLES127 - FEBRUARY 2005
PVDD 10 GVDD 10 F 10 TAS5152DKD 100 nF Microcontroller 0 Optional BKND_ERR 4 PWM_P_1 VALID PWM_M_1 30 k 7 8 GND 9 AGND 100 nF 10 VREG 11 M3 M2 M1 PWM_C RESET_CD 16 1 GVDD 10 F 10 100 nF PWM_D 17 VDD 18 GVDD_C 100 nF GVDD_D PVDD 100 nF 10 nF 50 V 3.3 1000 F 50 V BST_D 19 33 nF PVDD_D 20 100 nF 50 V BST_C 26 PVDD_C 25 OUT_C 24 GND_C 23 GND_D 22 OUT_D 21 47 F 50 V 10 H@10 A 10 H@10 A 33 nF BST_B 27 PVDD_B 28 33 nF 100 nF 50 V 100 nF 50 V 47 F 50 V 47 F 50 V 5 6 PWM_B OC_ADJ GND_B 30 OUT_B 29 PWM_A RESET_AB OUT_A 32 GND_A 31 100 nF 100 V 1 2 3 GVDD_B OTW SD GVDD_A BST_A 34 PVDD_A 33 10 H@10 A 470 nF 63 V 100 nF 50 V 36 35 33 nF 10 H@10 A 100 nF 100 V 100 nF 47 F 50 V 3.3 10 nF 50 V 1000 F 50 V
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10 nF 50 V 3.3
3.3 10 nF 50 V
TAS5508
12 13 14 15
10
Figure 17. Typical Differential (2N) PBTL Application With AD Modulation Filters
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TAS5152
SLES127 - FEBRUARY 2005
PVDD 10 100 nF 47 F 50 V TAS5152DKD 100 nF 3.3 10 nF 50 V 1000 F 50 V
GVDD 10 F 10 36 35 OTW SD PWM_A 5 6 No connect 30 k PWM_B 7 8 GND 9 AGND 100 nF 10 VREG 11 M3 M2 M1 PWM_C RESET_CD 16 1 GVDD 10 F 10 100 nF No connect 17 VDD 18 GVDD_C 100 nF GVDD_D BST_D 19 100 nF PWM_D PVDD_D 20 BST_C 26 PVDD_C 25 OUT_C 24 GND_C 23 GND_D 22 OUT_D 21 BST_B 27 PVDD_B 28 OC_ADJ GND_B 30 OUT_B 29 RESET_AB BST_A 34 PVDD_A 33 OUT_A 32 GND_A 31
Microcontroller 0 Optional BKND_ERR
1 2 3 4
GVDD_B
GVDD_A
33 nF 100 nF 50 V 10 H@10 A
PWM_P_1 VALID
10 H@10 A 100 nF 100 V
10 nF 50 V 3.3
33 nF
100 nF 50 V 100 nF 50 V
47 F 50 V 47 F 50 V
470 nF 63 V
33 nF
TAS5508
100 nF 100 V
3.3 10 nF 50 V
12 13 14 No connect 15
10 H@10 A
10 H@10 A
100 nF 50 V 33 nF
47 F 50 V
PVDD 3.3 10 nF 50 V 1000 F 50 V
10
Figure 18. Typical Non-Differential (1N) PBTL Application
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TAS5152
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THEORY OF OPERATION
POWER SUPPLIES
To facilitate system design, the TAS5152 needs only a 12-V supply in addition to the (typically) 35-V power-stage supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog circuitry. Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is accommodated by built-in bootstrap circuitry requiring only a few external capacitors. In order to provide outstanding electrical and acoustical characteristics, the PWM signal path including gate drive and output stage is designed as identical, independent half-bridges. For this reason, each half-bridge has separate gate drive supply (GVDD_X), bootstrap pins (BST_X), and power-stage supply pins (PVDD_X). Furthermore, an additional pin (VDD) is provided as supply for all common circuits. Although supplied from the same 12-V source, it is highly recommended to separate GVDD_A, GVDD_B, GVDD_C, GVDD_D, and VDD on the printed-circuit board (PCB) by RC filters (see application diagram for details). These RC filters provide the recommended high-frequency isolation. Special attention should be paid to placing all decoupling capacitors as close to their associated pins as possible. In general, inductance between the power supply pins and decoupling capacitors must be avoided. (See reference board documentation for additional information.) For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin (BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is charged through an internal diode connected between the gate-drive power-supply pin (GVDD_X) and the bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM switching frequencies in the range 352 kHz to 384 kHz, it is recommended to use 33-nF ceramic capacitors, size 0603 or 0805, for the bootstrap supply. These 33-nF capacitors ensure sufficient energy storage, even during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during the remaining part of the PWM cycle. In an application running at a reduced switching frequency, generally 192 kHz, the bootstrap capacitor might need to be increased in value. Special attention should be paid to the power-stage power supply; this includes component selection, PCB placement and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_X). For optimal electrical performance, EMI compliance, and
20
system reliability it is important that each PVDD_X pin is decoupled with a 100-nF ceramic capacitor placed as close as possible to each supply pin. It is recommended to follow the PCB layout of the TAS5152 reference design. For additional information on recommended power supply and required components, see the application diagrams given previously in this data sheet. The 12-V supply should be from a low-noise, low-output-impedance voltage regulator. Likewise, the 35-V power-stage supply is assumed to have low output impedance and low noise. The power-supply sequence is not critical as facilitated by the internal power-on-reset circuit. Moreover, the TAS5152 is fully protected against erroneous power-stage turnon due to parasitic gate charging. Thus, voltage-supply ramp rates (dV/dt) are non-critical within the specified range (see the Recommended Operating Conditions section of this data sheet).
SYSTEM POWER-UP/POWER-DOWN SEQUENCE
Powering Up
The TAS5152 does not require a power-up sequence. The outputs of the H-bridges remain in a high-impedance state until the gate-drive supply voltage (GVDD_X) and VDD voltage are above the undervoltage protection (UVP) voltage threshold (see the Electrical Characteristics section of this data sheet). Although not specifically required, it is recommended to hold RESET_AB and RESET_CD in a low state while powering up the device. This allows an internal circuit to charge the external bootstrap capacitors by enabling a weak pulldown of the half-bridge output. When the TAS5152 is being used with TI PWM modulators such as the TAS5508, no special attention to the state of RESET_AB and RESET_CD is required, provided that the chipset is configured as recommended.
Powering Down
The TAS5152 does not require a power-down sequence. The device remains fully operational as long as the gate-drive supply (GVDD_X) voltage and VDD voltage are above the undervoltage protection (UVP) voltage threshold (see the Electrical Characteristics section of this data sheet). Although not specifically required, it is a good practice to hold RESET_AB and RESET_CD low during power down, thus preventing audible artifacts including pops or clicks. When the TAS5152 is being used with TI PWM modulators such as the TAS5508, no special attention to the state of RESET_AB and RESET_CD is required, provided that the chipset is configured as recommended.
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TAS5152
SLES127 - FEBRUARY 2005
ERROR REPORTING
The SD and OTW pins are both active-low, open-drain outputs. Their function is for protection-mode signaling to a PWM controller or other system-control device. Any fault resulting in device shutdown is signaled by the SD pin going low. Likewise, OTW goes low when the device junction temperature exceeds 125C (see the following table).
Use of TAS5152 in High-Modulation-Index Capable Systems
This device requires at least 50 ns of low time on the output per 384-kHz PWM frame rate in order to keep the bootstrap capacitors charged. As an example, if the modulation index is set to 99.2% in the TAS5508, this setting allows PWM pulse durations down to 20 ns. This signal, which does not meet the 50-ns requirement, is sent to the PWM_x pin and this low-state pulse time does not allow the bootstrap capacitor to stay charged. In this situation, the low voltage across the bootstrap capacitor can cause a failure of the high-side MOSFET transistor, especially when driving a low-impedance load. The TAS5152 device requires limiting the TAS5508 modulation index to 96.1% to keep the bootstrap capacitor charged under all signals and loads. Therefore, TI strongly recommends using a TI PWM processor, such as TAS5508 or TAS5086, with the modulation index set at 96.1% to interface with TAS5152.
SD 0 0 1 1
OTW 0 1 0 1
DESCRIPTION Overtemperature (OTE) or overload (OLP) or undervoltage (UVP) Overload (OLP) or undervoltage (UVP) Junction temperature higher than 125C (overtemperature warning) Junction temperature lower than 125C and no OLP or UVP faults (normal operation)
Note that asserting either RESET_AB or RESET_CD low forces the SD signal high, independent of faults being present. TI recommends to monitoring the OTW signal using the system microcontroller and responding to an overtemperature warning signal by, e.g., turning down the volume to prevent further heating of the device resulting in device shutdown (OTE). To reduce external component count, an internal pullup resistor to 3.3V is provided on both SD and OTW outputs. Level compliance for 5-V logic can be obtained by adding external pullup resistors to 5 V (see the Electrical Characteristics section of this data sheet for further specifications).
Overcurrent (OC) Protection With Current Limiting and Overload Detection
The device has independent, fast-reacting current detectors with programmable trip threshold (OC threshold) on all high-side and low-side power-stage FETs. See the following table for OC-adjust resistor values. The detector outputs are closely monitored by two protection systems. The first protection system controls the power stage in order to prevent the output current from further increasing, i.e., it performs a current-limiting function rather than prematurely shutting down during combinations of high-level music transients and extreme speaker load impedance drops. If the high-current situation persists, i.e., the power stage is being overloaded, a second protection system triggers a latching shutdown, resulting in the power stage being set in the high-impedance (Hi-Z) state. Current limiting and overload protection are independent for the half-bridges A and B and, respectively, C and D. That is, if the bridge-tied load between half-bridges A and B causes an overload fault, only half-bridges A and B are shut down.
DEVICE PROTECTION SYSTEM
TAS5152 contains advanced protection circuitry carefully designed to facilitate system integration and ease of use, as well as to safeguard the device from permanent failure due to a wide range of fault conditions such as short circuits, overload, overtemperature, and undervoltage. The TAS5152 responds to a fault by immediately setting the power stage in a high-impedance state (Hi-Z) and asserting the SD pin low. In situations other than overload, the device automatically recovers when the fault condition has been removed, i.e., the junction temperature has dropped or the voltage supply has increased. For highest possible reliability, recovering from an overload fault requires external reset of the device (see the Device Reset section of this data sheet) no sooner than 1 second after the shutdown.
D For the lowest-cost bill of materials in terms
of component selection, the OC threshold measure should be limited, considering the power output requirement and minimum load impedance. Higher-impedance loads require a lower OC threshold. The demodulation-filter inductor must retain at least 3 H of inductance at twice the OC threshold setting.
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D
TAS5152
SLES127 - FEBRUARY 2005
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Unfortunately, most inductors have decreasing inductance with increasing temperature and increasing current (saturation). To some degree, an increase in temperature naturally occurs when operating at high output currents, due to core losses and the DC resistance of the inductor's copper winding. A thorough analysis of inductor saturation and thermal properties is strongly recommended. Setting the OC threshold too low might cause issues such as lack of enough output power and/or unexpected shutdowns due to too-sensitive overload detection. In general, it is recommended to follow closely the external component selection and PCB layout as given in the Application section. For added flexibility, the OC threshold is programmable within a limited range using a single external resistor connected between the OC_ADJ pin and AGND. (See the Electrical Characteristics section of this data sheet for information on the correlation between programmingresistor value and the OC threshold.) It should be noted that a properly functioning overcurrent detector assumes the presence of a properly designed demodulation filter at the power-stage output. Short-circuit protection is not provided directly at the output pins of the power stage but only on the speaker terminals (after the demodulation filter). It is required to follow certain guidelines when selecting the OC threshold and an appropriate demodulation inductor:
OC-Adjust Resistor Values (kW) 15 22 27 39 47 69 Max. Current Before OC Occurs (A) 10.8 9.4 8.6 6.4 6 4.7
resulting in all half-bridge outputs being set in the high-impedance state (Hi-Z) and SD being asserted low. OTE is latched in this case. To clear the OTE latch, both RESET_AB and RESET_CD must be asserted. Thereafter, the device resumes normal operation.
Undervoltage Protection (UVP) and Power-On Reset (POR)
The UVP and POR circuits of the TAS5152 fully protect the device in any power-up/down and brownout situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are fully operational when the GVDD_X and VDD supply voltages reach 9.8 V (typical). Although GVDD_X and VDD are independently monitored, a supply voltage drop below the UVP threshold on any VDD or GVDD_X pin results in all half-bridge outputs immediately being set in the high-impedance state (Hi-Z) and SD being asserted low. The device automatically resumes operation when all supply voltages have increased above the UVP threshold.
DEVICE RESET
Two reset pins are provided for independent control of half-bridges A/B and C/D. When RESET_AB is asserted low, all four power-stage FETs in half-bridges A and B are forced into a high-impedance state (Hi-Z). Likewise, asserting RESET_CD low forces all four power-stage FETs in half-bridges C and D into a high-impedance state. Thus, both reset pins are well suited for hard-muting the power stage if needed. In BTL modes, to accommodate bootstrap charging prior to switching start, asserting the reset inputs low enables weak pulldown of the half-bridge outputs. In the SE mode, the weak pulldowns are not enabled, and it is therefore recommended to ensure bootstrap capacitor charging by providing a low pulse on the PWM inputs when reset is asserted high. Asserting either reset input low removes any fault information to be signalled on the SD output, i.e., SD is forced high. A rising-edge transition on either reset input allows the device to resume operation after an overload fault.
Overtemperature Protection
The TAS5152 has a two-level temperature-protection system that asserts an active-low warning signal (OTW) when the device junction temperature exceeds 125C (nominal) and, if the device junction temperature exceeds 155C (nominal), the device is put into thermal shutdown,
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TAS5152
SLES127 - FEBRUARY 2005
MECHANICAL DATA
23
PACKAGE OPTION ADDENDUM
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30-Mar-2005
PACKAGING INFORMATION
Orderable Device TAS5152DKD TAS5152DKDR
(1)
Status (1) ACTIVE ACTIVE
Package Type SSOP SSOP
Package Drawing DKD DKD
Pins Package Eco Plan (2) Qty 36 36 29 500 Pb-Free (RoHS) Pb-Free (RoHS)
Lead/Ball Finish CU SNBI CU SNBI
MSL Peak Temp (3) Level-4-260C-72 HR/ Level-2-220C-1 YEAR Level-4-260C-72 HR/ Level-2-220C-1 YEAR
The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
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